library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;

entity ecc is
  port ( rst : in  std_logic;
         clk : in  std_logic );
end entity;

architecture arch of ecc is
  component ecc_core is
    port ( rst       : in  std_logic;
           clk       : in  std_logic;
           start     : in  std_logic;
           done      : out std_logic;
           dmem_addr : out std_logic_vector(  6 downto 0);
           dmem_out  : in  std_logic_vector(232 downto 0);
           dmem_we   : out std_logic;
           dmem_in   : out std_logic_vector(232 downto 0) );
  end component;

  signal start : std_logic;
  signal done  : std_logic;

  signal debug_addr : std_logic_vector(  6 downto 0);
  signal debug_out  : std_logic_vector(232 downto 0);

  signal dmem_addr : std_logic_vector(  6 downto 0);
  signal dmem_out  : std_logic_vector(232 downto 0);
  signal dmem_we   : std_logic;
  signal dmem_in   : std_logic_vector(232 downto 0);
begin
  dmem : altsyncram
    generic map ( width_a   => 233,
                  widthad_a => 7,
                  width_b   => 233,
                  widthad_b => 7,
                  init_file => "data_mem.mif" )
    port map ( address_a => debug_addr,
               data_a    => (232 downto 0 => '0'),
               wren_a    => '0',
               q_a       => debug_out,
               clock0    => clk,
               address_b => dmem_addr,
               data_b    => dmem_in,
               wren_b    => dmem_we,
               q_b       => dmem_out,
               clock1    => clk );

  core : ecc_core
    port map ( rst   => rst,
               clk   => clk,
               start => start,
               done  => done,
               dmem_addr => dmem_addr,
               dmem_out  => dmem_out,
               dmem_we   => dmem_we,
               dmem_in   => dmem_in );
end architecture;