library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library altera_mf;
use altera_mf.altera_mf_components.all;

entity ecc_core is
  port ( rst       : in  std_logic;
         clk       : in  std_logic;
         start     : in  std_logic;
         done      : out std_logic;
         dmem_addr : out std_logic_vector(  6 downto 0);
         dmem_out  : in  std_logic_vector(232 downto 0);
         dmem_we   : out std_logic;
         dmem_in   : out std_logic_vector(232 downto 0) );
end entity;

architecture arch of ecc_core is
  type state_t is (sIdle, sFetch, sDecode, sLoadA, sLoadB, sExec, sDone);
  signal state : state_t := sIdle;

  signal pc       : std_logic_vector(9 downto 0) := "0000000000";
  signal loop_cnt : std_logic_vector(7 downto 0) := X"00";
  signal cyc_cnt  : std_logic_vector(7 downto 0) := X"00";

  signal instr : std_logic_vector(27 downto 0);

  -- Add some stuff!

begin
  process(clk)
  begin
    if rst = '1' then
      state    <= sIdle;
      pc       <= "0000000000";
      loop_cnt <= X"00";
      cyc_cnt  <= X"00";
    elsif clk'event and clk = '1' then
      if state = sIdle then
        if start = '1' then
          state <= sFetch;
          pc    <= "0000000000";
        end if;

      elsif state = sFetch then
        state <= sDecode;

      elsif state = sDecode then
        -- Add some stuff!

      elsif state = sLoadA then
        -- Add some stuff!

      elsif state = sLoadB then
        -- Add some stuff!

      elsif state = sExec then
        -- Add some stuff!

      elsif state = sDone then
        -- Add some stuff!

      end if;
    end if;
  end process;

  dmem_addr <= instr(22 downto 16) when state = sDecode else
               instr(14 downto  8) when state = sLoadA  else
               instr( 6 downto  0);

  done <= '1' when state = sDone else
          '0';

  -- Add some stuff!

  imem : altsyncram
    generic map ( operation_mode => "ROM",
                  width_a        => 28,
                  widthad_a      => 10,
                  init_file      => "instr_mem.mif" )
    port map ( address_a => pc,
               q_a       => instr,
               clock0    => clk );
end architecture;